HEY GUYS I HAD DEVELOPED VHDL CODE TO FIND GCD YOU CAN GO THROUGH IT
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity gcd is
port( X: in unsigned(3 downto 0);
Y: in unsigned(3 downto 0);
o: out unsigned(3 downto 0)
);
end gcd;
architecture gcd of gcd is
begin
process(X,Y)
variable tmp_X, tmp_Y: unsigned(3 downto 0);
begin
tmp_X := X;
tmp_Y := Y;
for i in 0 to 15 loop
if (tmp_X/=tmp_Y) then
if (tmp_X < tmp_Y) then
tmp_Y := tmp_Y - tmp_X;
else
tmp_X := tmp_X - tmp_Y;
exit loop;
end if;
else
o<= tmp_X;
end if;
end loop;
end process;
end gcd;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity gcd is
port( X: in unsigned(3 downto 0);
Y: in unsigned(3 downto 0);
o: out unsigned(3 downto 0)
);
end gcd;
architecture gcd of gcd is
begin
process(X,Y)
variable tmp_X, tmp_Y: unsigned(3 downto 0);
begin
tmp_X := X;
tmp_Y := Y;
for i in 0 to 15 loop
if (tmp_X/=tmp_Y) then
if (tmp_X < tmp_Y) then
tmp_Y := tmp_Y - tmp_X;
else
tmp_X := tmp_X - tmp_Y;
exit loop;
end if;
else
o<= tmp_X;
end if;
end loop;
end process;
end gcd;
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