VHDL CODE FOR 4*4 RAM

Hey guys i had developed vhdl code for 4*4 Ram .you can go through it !!


4*4 RAM


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------

entity SRAM is
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(1 downto 0);
Write_Addr: in std_logic_vector(1 downto 0);
Data_in: in std_logic_vector(3 downto 0);
Data_out: out std_logic_vector(3 downto 0)
);
end SRAM;

--------------------------------------------------------------

architecture behav of SRAM is

type ram_type is array (0 to 3) of
std_logic_vector(3 downto 0) ;
signal tmp_ram : ram_type := ( "0000", "0011", "0111", "0101" ) ;

begin

    -- Read Functional Section
    process(Clock, Read)
    begin
if (Clock'event and Clock='1') then
   if Enable='1' then
if Read='1' then
   Data_out <= tmp_ram(conv_integer(Read_Addr));
end if;
   end if;
end if;
    end process;

    -- Write Functional Section
    process(Clock, Write)
    begin
if (Clock'event and Clock='1') then
   if Enable='1' then
if Write='1' then
   tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
   end if;
end if;
    end process;

end behav;

Hope you like it!!!!!!