VHDL CODE FOR ROM

HEY GUYS I HAD DEVELOPED VHDL CODE FOR ROM !! GO THROUGH IT HOPE IT MAY HELPFUL TO YOU.

ROM

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;  

use ieee.std_logic_unsigned.all;

entity ROM is

port( Clock   : in std_logic;

Reset : in std_logic;

Enable : in std_logic;

Read : in std_logic;

Address : in std_logic_vector(1 downto 0);

Data_out: out std_logic_vector(3 downto 0)

);

end ROM;

--------------------------------------------------------------

architecture Behav of ROM is

    type ROM_Array is array (0 to 3) 

of std_logic_vector(3 downto 0);

    constant Content: ROM_Array := ("0000","0010","1111","1101");       

begin

    process(Clock, Reset, Read, Address)

    begin

        if( Reset = '1' ) then

   Data_out <= "XXXX";

        elsif( Clock'event and Clock = '1' ) then

   if Enable = '1' then

if( Read = '1' ) then

   Data_out <= Content(conv_integer(Address));

            end if;

   end if;

        end if;

    end process;

end Behav;